a. Adjust the (negative) programmable delay in the FCCC (as described in “Clocking in SmartFusion2” section on
page 127 ) until External Setup violations go away in Max Delay Analysis, but not so far as to introduce Internal
Setup violations.
b. Adjust all input delays until hold violations on paths ending at input ports go away in Min Delay Analysis, using
the -IN_DELAY x switch in the PDC.
Notes on Synthesis:
To ensure that timing is met, it is important to be able to push as many flip-flops as possible into the I/O registers. To
accomplish this, keep the max fanout on output registers at 1 during synthesis. This can be accomplished using the
following SDC attributes in the Synthesis constraint file (The instance name need to match with the instance name of
your design):
define_attribute
{{i:UCORE.MAKE_TARGET.DATAPATHE64.MAKE_DATAPATH_REGISTERS.AD_REGS[31:0]}}
{syn_preserve} {1}
define_attribute {{i:UCORE.MAKE\.UDMA.CBEN_PAD[7:0]}} {syn_replicate} {1}
define_attribute {{i:UCORE.MAKE\.UDMA.CBEN_PAD[7:0]}} {syn_maxfan} {1}
define_attribute
{{i:UCORE.MAKE_TARGET.DATAPATHE.MAKE_DATAPATH_REGISTERS.AD_REGS[31:0]}} {syn_preserve}
{1}
define_attribute {{i:UCORE.MAKE_TARGET.BurstE.UA1\.MAKE_ACK64_OUT.Q_INT}}
{syn_replicate} {1}
define_attribute {{i:UCORE.MAKE\.UDMA.MAKE_REQ64N1.Q_INT}} {syn_replicate} {1}
define_attribute {{i:UCORE.MAKE\.UDMA.MAKE_REQ64N1.Q_INT}} {syn_maxfan} {1}
define_attribute {{i:UCORE.MAKE_TARGET.BurstE.UA1\.MAKE_ACK64_OUT.Q_INT}} {syn_maxfan}
{1}
define_attribute {{i:UCORE.MAKE_TARGET.BurstE.UM1\.MAKE_IRDY_OUT.Q_INT}}
{syn_replicate} {1}
define_attribute {{i:UCORE.MAKE_TARGET.BurstE.UM1\.MAKE_IRDY_OUT.Q_INT}} {syn_maxfan}
{1}
132
v4.0
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